// Verilated -*- C++ -*-
// DESCRIPTION: Verilator output: Design implementation internals
// See VysyxSoCFull.h for the primary calling header

#include "VysyxSoCFull.h"
#include "VysyxSoCFull__Syms.h"

#include "verilated_dpi.h"

VL_INLINE_OPT void VysyxSoCFull::_sequent__TOP__36(VysyxSoCFull__Syms* __restrict vlSymsp) {
    VL_DEBUG_IF(VL_DBG_MSGF("+    VysyxSoCFull::_sequent__TOP__36\n"); );
    VysyxSoCFull* const __restrict vlTOPp VL_ATTR_UNUSED = vlSymsp->TOPp;
    // Variables
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    // Body
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_param)) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94268: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94268, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__full)
                                ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_corrupt)
                                : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_corrupt))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel AccessAck is corrupt (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__full)
                                ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_corrupt)
                                : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_corrupt))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94292: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94292, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ (((((((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U))) 
                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                  >> 3U)))) 
                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                 >> 3U)))) 
                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U)))) 
                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                               >> 3U)))) 
                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                              >> 3U)))) 
                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                             >> 3U)))) 
                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                            >> 3U)))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ (((((((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U))) 
                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                  >> 3U)))) 
                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                 >> 3U)))) 
                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U)))) 
                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                               >> 3U)))) 
                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                              >> 3U)))) 
                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                             >> 3U)))) 
                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                            >> 3U)))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94316: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94316, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_param)) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel AccessAckData carries invalid param (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_param)) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94340: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94340, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_denied)) 
                            | ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__full)
                                ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_corrupt)
                                : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_corrupt))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_denied)) 
                            | ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__full)
                                ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_corrupt)
                                : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_corrupt))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94364: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94364, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ (((((((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U))) 
                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                  >> 3U)))) 
                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                 >> 3U)))) 
                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U)))) 
                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                               >> 3U)))) 
                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                              >> 3U)))) 
                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                             >> 3U)))) 
                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                            >> 3U)))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel HintAck carries invalid source ID (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ (((((((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U))) 
                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                  >> 3U)))) 
                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                 >> 3U)))) 
                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                                >> 3U)))) 
                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                               >> 3U)))) 
                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                              >> 3U)))) 
                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                             >> 3U)))) 
                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                                            >> 3U)))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94388: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94388, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_param)) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel HintAck carries invalid param (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_param)) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94412: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94412, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__full)
                                ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_corrupt)
                                : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_corrupt))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel HintAck is corrupt (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                      & (2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__full)
                                ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_corrupt)
                                : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_corrupt))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94436: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94436, "");
    }
    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
                      & (4U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_opcode))) 
                     & (~ ((((0ULL == (0x180000000ULL 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94460: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94484: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94652: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94676: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                     & (~ ((((0xcU >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
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                                      | (1U == (7U 
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                                     | (2U == (7U & 
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                                    | (3U == (7U & 
                                              ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                   | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                  | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                            & ((6U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel carries Release type unsupported by manager (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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                                      | (1U == (7U 
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                                     | (2U == (7U & 
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                                    | (3U == (7U & 
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                                   | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                  | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                 >> 3U)))) 
                                | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                            & ((6U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94700: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                             & (6U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size))) 
                            & ((0xcU >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
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                                  | (0ULL == (0x180000000ULL 
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                                  | (0ULL == (0x180000000ULL 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94724: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94748: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                     & (~ ((0U == (0xffU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_address_T_1) 
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                     & (~ ((5U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_param)) 
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                                      | (1U == (7U 
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                                                   >> 3U)))) 
                                     | (2U == (7U & 
                                               ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                >> 3U)))) 
                                    | (3U == (7U & 
                                              ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                               >> 3U)))) 
                                   | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                   >> 3U)))) 
                                  | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                  >> 3U)))) 
                                 | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                 >> 3U)))) 
                                | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                >> 3U))))) 
                            & ((6U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
                               & (0ULL == (0x1fffff000ULL 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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                     & (~ ((((0xcU >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
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                                      | (1U == (7U 
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                                     | (2U == (7U & 
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                                    | (3U == (7U & 
                                              ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                               >> 3U)))) 
                                   | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                   >> 3U)))) 
                                  | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                  >> 3U)))) 
                                 | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                 >> 3U)))) 
                                | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                >> 3U))))) 
                            & ((6U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
                               & (0ULL == (0x1fffff000ULL 
                                           & (QData)((IData)(
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                                                              ^ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_address_T_1)))))))) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94844: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                     & (~ ((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             & (6U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size))) 
                            & ((0xcU >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
                               & (((0ULL == (0x1fffff000ULL 
                                             & (QData)((IData)(
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                                   | (0ULL == (0x1c0000000ULL 
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                                  | (0ULL == (0x180000000ULL 
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                     & (~ ((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             & (6U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size))) 
                            & ((0xcU >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
                               & (((0ULL == (0x1fffff000ULL 
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                                   | (0ULL == (0x1c0000000ULL 
                                               & (QData)((IData)(
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                                  | (0ULL == (0x180000000ULL 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94868: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                     & (~ (((((((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                 >> 3U)))) 
                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                >> 3U)))) 
                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                             >> 3U)))) 
                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                     & (~ (((((((((0U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                  >> 3U)))) 
                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                 >> 3U)))) 
                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                >> 3U)))) 
                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                               >> 3U)))) 
                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                              >> 3U)))) 
                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                             >> 3U)))) 
                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94892: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 94892, "");
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                     & (~ ((2U <= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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                     & (~ ((2U <= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size)) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94916: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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                     & (~ ((0U == (0xffU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_address_T_1) 
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                                                     << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size))))))) 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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                     & (~ ((0U == (0xffU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_address_T_1) 
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                     & (~ ((5U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_param)) 
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                     & (~ ((5U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_param)) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:94964: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                     & (~ ((((0ULL == (0x180000000ULL 
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                             | (0ULL == (0x1c0000000ULL 
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                            | (0ULL == (0x1fffff000ULL 
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                                       & (QData)((IData)(
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                             | (0ULL == (0x1c0000000ULL 
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                            | (0ULL == (0x1fffff000ULL 
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                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
                                                >> 3U)))) 
                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                  | (1U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                 | (2U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                            | (7U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95012: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel AccessAck carries invalid param (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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                                | (3U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                               | (4U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                              | (5U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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                             | (6U == (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95108: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95204: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95252: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95300: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95324: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95348: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95468: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel source changed within multibeat operation (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95492: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel denied changed with multibeat operation (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95516: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel opcode changed within multibeat operation (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95540: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel param changed within multibeat operation (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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                     & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_param) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95564: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel size changed within multibeat operation (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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                     & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_bits_size) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95588: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel source changed within multibeat operation (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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                     & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_source_T) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95612: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'C' channel address changed with multibeat operation (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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    if (VL_UNLIKELY((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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                     & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___io_c_bits_address_T_1) 
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                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95636: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                     & (~ ((~ (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight 
                                       >> (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source)))) 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'A' channel re-used a source ID (connected at ChipLink.scala:71:16)\n    at Monitor.scala:42 assert(cond, message)\n");
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                     & (~ ((~ (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight 
                                       >> (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source)))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95660: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                      & (6U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                     & (~ (((IData)((vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight 
                                     >> (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source))) 
                            | (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
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        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel acknowledged for nothing inflight (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
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                     & (~ (((IData)((vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight 
                                     >> (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source))) 
                            | (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
                                & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
                               & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source) 
                                  == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source)))) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95684: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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    if (VL_UNLIKELY((((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
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                       & (6U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                      & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
                          & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
                         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source) 
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                     & (~ ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
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                                  ? 4U : ((6U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_opcode))
                                           ? 4U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_42)))) 
                            | ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
                               == ((7U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_opcode))
                                    ? 4U : ((6U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_opcode))
                                             ? 5U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_42))))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel contains improper opcode response (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                        & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__d_first_counter_1))) 
                       & (6U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                      & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
                          & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
                         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source) 
                            == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source)))) 
                     & (~ ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
                             == ((7U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_opcode))
                                  ? 4U : ((6U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_opcode))
                                           ? 4U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_42)))) 
                            | ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
                               == ((7U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_opcode))
                                    ? 4U : ((6U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_opcode))
                                             ? 5U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_42))))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95708: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 95708, "");
    }
    if (VL_UNLIKELY((((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                        & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__d_first_counter_1))) 
                       & (6U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                      & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
                          & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
                         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source) 
                            == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source)))) 
                     & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_size) 
                            == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_size)) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel contains improper response size (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    if (VL_UNLIKELY((((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                        & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__d_first_counter_1))) 
                       & (6U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                      & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
                          & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
                         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source) 
                            == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source)))) 
                     & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_size) 
                            == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_size)) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95732: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 95732, "");
    }
    __Vtemp3752[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3752[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3752[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3752[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3752[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3752[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3752[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3752[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3753, __Vtemp3752);
    __Vtemp3756[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3756[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3756[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3756[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3756[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3756[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3756[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3756[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3757, __Vtemp3756);
    __Vtemp3760[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3760[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3760[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3760[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3760[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3760[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3760[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3760[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3761, __Vtemp3760);
    __Vtemp3764[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3764[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3764[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3764[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3764[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3764[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3764[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3764[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3765, __Vtemp3764);
    if (VL_UNLIKELY((((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                        & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__d_first_counter_1))) 
                       & (6U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                      & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
                             & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
                            & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source) 
                               == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source))))) 
                     & (~ ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
                             == ((7U == (7U & __Vtemp3753[0U]))
                                  ? 4U : ((6U == (7U 
                                                  & __Vtemp3757[0U]))
                                           ? 4U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_58)))) 
                            | ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
                               == ((7U == (7U & __Vtemp3761[0U]))
                                    ? 4U : ((6U == 
                                             (7U & 
                                              __Vtemp3765[0U]))
                                             ? 5U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_58))))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed: 'D' channel contains improper opcode response (connected at ChipLink.scala:71:16)\n    at Monitor.scala:49 assert(cond, message)\n");
    }
    __Vtemp3768[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3768[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3768[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3768[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3768[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3768[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3768[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3768[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3769, __Vtemp3768);
    __Vtemp3772[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3772[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3772[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3772[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3772[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3772[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3772[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3772[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3773, __Vtemp3772);
    __Vtemp3776[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3776[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3776[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3776[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3776[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3776[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3776[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3776[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3777, __Vtemp3776);
    __Vtemp3780[0U] = (__Vconst345[0U] & (((__Vconst346[1U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[0U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[0U]) 
                                             >> 1U)));
    __Vtemp3780[1U] = (__Vconst345[1U] & (((__Vconst346[2U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[1U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[1U]) 
                                             >> 1U)));
    __Vtemp3780[2U] = (__Vconst345[2U] & (((__Vconst346[3U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[2U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[2U]) 
                                             >> 1U)));
    __Vtemp3780[3U] = (__Vconst345[3U] & (((__Vconst346[4U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[3U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[3U]) 
                                             >> 1U)));
    __Vtemp3780[4U] = (__Vconst345[4U] & (((__Vconst346[5U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[4U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[4U]) 
                                             >> 1U)));
    __Vtemp3780[5U] = (__Vconst345[5U] & (((__Vconst346[6U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[5U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[5U]) 
                                             >> 1U)));
    __Vtemp3780[6U] = (__Vconst345[6U] & (((__Vconst346[7U] 
                                            & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                           << 0x1fU) 
                                          | ((__Vconst346[6U] 
                                              & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[6U]) 
                                             >> 1U)));
    __Vtemp3780[7U] = (__Vconst345[7U] & ((__Vconst346[7U] 
                                           & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___a_opcode_lookup_T_1[7U]) 
                                          >> 1U));
    VL_EXTEND_WW(256,255, __Vtemp3781, __Vtemp3780);
    if (VL_UNLIKELY((((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1_io_in_d_valid) 
                        & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__d_first_counter_1))) 
                       & (6U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))) 
                      & (~ (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_o_valid) 
                             & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
                            & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract_io_i_bits_source) 
                               == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source))))) 
                     & (~ ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
                             == ((7U == (7U & __Vtemp3769[0U]))
                                  ? 4U : ((6U == (7U 
                                                  & __Vtemp3773[0U]))
                                           ? 4U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_58)))) 
                            | ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode) 
                               == ((7U == (7U & __Vtemp3777[0U]))
                                    ? 4U : ((6U == 
                                             (7U & 
                                              __Vtemp3781[0U]))
                                             ? 5U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_58))))) 
                           | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95756: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 95756, "");
    }
    VL_SHIFTR_WWI(512,512,9, __Vtemp3782, vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_sizes, 
                  ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source) 
                   << 3U));
    __Vtemp3785[0U] = (__Vconst141[0U] & (((__Vconst3625[1U] 
                                            & __Vtemp3782[1U]) 
                                           << 0x1fU) 
                                          | ((__Vconst3625[0U] 
                                              & __Vtemp3782[0U]) 
                                             >> 1U)));
    __Vtemp3785[1U] = (__Vconst141[1U] & (((__Vconst3625[2U] 
                                            & __Vtemp3782[2U]) 
                                           << 0x1fU) 
                                          | ((__Vconst3625[1U] 
                                              & __Vtemp3782[1U]) 
                                             >> 1U)));
    __Vtemp3785[2U] = (__Vconst141[2U] & (((__Vconst3625[3U] 
                                            & __Vtemp3782[3U]) 
                                           << 0x1fU) 
                                          | ((__Vconst3625[2U] 
                                              & __Vtemp3782[2U]) 
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                         & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
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                         & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__a_first_counter_1))) 
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                               | (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__watchdog 
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                               | (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__watchdog 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95874: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95898: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
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                      & ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_c_valid) 
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95968: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                                                  (1ULL 
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                                                  (1ULL 
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                                             | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:95992: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:96016: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:96040: Assertion failed in %NTestHarness.ldut.fpga.chiplink.mbypass.monitor_1\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
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        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 40887, "");
    }
    vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_if_stage__DOT__pcD_dff__DOT__qout_r 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_if_stage__DOT__pcD_dff__DOT__qout_r;
    vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4frag__DOT__in_wdeq__DOT__ram_data__v0 = 0U;
    if (VL_UNLIKELY((1U & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar_auto_out_1_arvalid) 
                                  & (2U < (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__if_size)))) 
                              | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed\n    at AXI4ToAPB.scala:70 assert(!(ar.valid && ar.bits.size > \"b10\".U))\n");
    }
    if (VL_UNLIKELY((1U & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar_auto_out_1_arvalid) 
                                  & (2U < (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__if_size)))) 
                              | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:85340: Assertion failed in %NTestHarness.ldut.asic.axi42apb\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 85340, "");
    }
    if (VL_UNLIKELY((1U & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar_auto_out_1_awvalid) 
                                  & (2U < (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__if_size)))) 
                              | (IData)(vlTOPp->reset)))))) {
        VL_FWRITEF(0x80000002U,"Assertion failed\n    at AXI4ToAPB.scala:71 assert(!(aw.valid && aw.bits.size > \"b10\".U))\n");
    }
    if (VL_UNLIKELY((1U & (~ ((~ ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar_auto_out_1_awvalid) 
                                  & (2U < (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__if_size)))) 
                              | (IData)(vlTOPp->reset)))))) {
        VL_WRITEF("[%0t] %%Error: ysyxSoCFull.v:85363: Assertion failed in %NTestHarness.ldut.asic.axi42apb\n",
                  64,VL_TIME_UNITED_Q(100),-9,vlSymsp->name());
        VL_STOP_MT("/home/zzdywc/Desktop/oscpu-zzd/projects/soc/build_test/vsrc/ysyxSoCFull.v", 85363, "");
    }
    vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_id_stage__DOT__instTypeE_dff__DOT__qout_r 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_id_stage__DOT__instTypeE_dff__DOT__qout_r;
    vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_csrfile__DOT__ITtime_dff__DOT__qout_r 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_csrfile__DOT__ITtime_dff__DOT__qout_r;
    vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_id_stage__DOT__pcE_dff__DOT__qout_r 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_id_stage__DOT__pcE_dff__DOT__qout_r;
    vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_ex_stage__DOT__jalbranch_dff__DOT__qout_r 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_ex_stage__DOT__jalbranch_dff__DOT__qout_r;
    vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_regfile__DOT__regs__v0 = 0U;
    vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__u_ysyx_210407_regfile__DOT__regs__v32 = 0U;
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__b_delay = 0U;
    vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram_R0_en;
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_ren 
        = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram_R0_en;
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_burst__v0 = 1U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_auto_in_d_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_data__v0 = 1U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem_R0_en) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__reg_R0_addr 
            = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                             >> 3U));
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT__ram_data__v0 = 1U;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__reg_dat8_w_reg 
        = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__reg_dat8_w;
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT__ram_strb__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_mask;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT__ram_strb__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_param 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_c_bits_param;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_param 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_c_bits_param;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___T_5) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__r_addr_1 
            = ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1_io_deq_bits_burst))
                ? vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1_io_deq_bits_addr
                : ((2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1_io_deq_bits_burst))
                    ? ((0x7fffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__inc_addr_1 
                                   & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___wrapMask_T_3 
                                      >> 8U))) | (~ 
                                                  ((~ vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1_io_deq_bits_addr) 
                                                   | (0x7fffU 
                                                      & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___wrapMask_T_3 
                                                         >> 8U)))))
                    : vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__inc_addr_1));
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___T_2) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__r_addr 
            = ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_bits_burst))
                ? vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_bits_addr
                : ((2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_bits_burst))
                    ? ((0x7fffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__inc_addr 
                                   & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___wrapMask_T_1 
                                      >> 8U))) | (~ 
                                                  ((~ vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_bits_addr) 
                                                   | (0x7fffU 
                                                      & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___wrapMask_T_1 
                                                         >> 8U)))))
                    : vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__inc_addr));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater__DOT__saved_mask 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_mask;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater__DOT__saved_mask 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_mask;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_resp__v0 
            = (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_denied) 
                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_auto_in_d_bits_corrupt))
                ? 2U : 0U);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_resp__v0 = 1U;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__r_len_1 
        = (0xffU & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___GEN_9));
    vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__r_len 
        = (0xffU & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___GEN_4));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__empty)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram_out_valid 
        = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q_io_enq_ready) 
           & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__atLeastTwo) 
              | ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq_io_deq_valid)) 
                 & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__empty)))));
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT__saved_denied 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_in_d_bits_denied;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_denied 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_denied;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT__saved_param 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_in_d_bits_param;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_param 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_param;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq_io_enq_bits_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_id__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_source 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_c_bits_source) 
               << 1U);
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_source 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_c_bits_source) 
               << 1U);
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_addr__v0 
            = (~ ((~ vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__addr) 
                  | (7U & (~ (0x3ffU & ((IData)(7U) 
                                        << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_bits_size)))))));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_addr__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_addr__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_echo_real_last__v0 
            = (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__len));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_echo_real_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_echo_real_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag_auto_out_awvalid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr__v0 
            = (~ ((~ vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__addr_1) 
                  | (7U & (~ (0x3ffU & ((IData)(7U) 
                                        << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1_io_deq_bits_size)))))));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag_auto_out_awvalid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_echo_real_last__v0 
            = (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__len_1));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_echo_real_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_echo_real_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT__saved_data 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_in_d_bits_data;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_data 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_data;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT___bid_reg_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__bid_reg = 0U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT___rid_reg_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__rid_reg = 0U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT___wdata_reg_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__wstrb_reg 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__cpu__DOT__cpu__DOT__u_ysyx_210407_rvcpu__DOT__RamWriteMask;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_29__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_30__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_31__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__d_first_counter_2 = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__d_first_counter_1 = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__d_first_counter = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__flight = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__flight = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xfU] 
            = __Vconst3802[0xfU];
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes_1[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T_5[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__flight 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__next_flight;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__flight 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__next_flight;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_sizes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_sizes_T[0xfU];
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_out_1_e_valid)
                                                    ? 1U
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_out_1_e_valid)
                                                    ? 1U
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_out_2_e_valid)
                                                    ? 1U
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_out_2_e_valid)
                                                    ? 1U
                                                    : 0U)))));
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__flight = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__flight = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_opcodes = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_opcodes = 0U;
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__flight 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__next_flight;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__flight 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__next_flight;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT___inflight_opcodes_T_2;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_23__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_24__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_25__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_26__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_27__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_28__DOT__maybe_full = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__ferr__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[0U] 
            = __Vconst3811[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[1U] 
            = __Vconst3811[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[2U] 
            = __Vconst3811[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[3U] 
            = __Vconst3811[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[4U] 
            = __Vconst3811[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[5U] 
            = __Vconst3811[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[6U] 
            = __Vconst3811[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[7U] 
            = __Vconst3811[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3811[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3811[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3811[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3811[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3811[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3811[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3811[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3811[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3811[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3811[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3811[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3811[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3811[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3811[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3811[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3811[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__ferr__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__ferr__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__ferr__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__ferr__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__ferr__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__err__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__bundleIn_0_d_bits_data_rdata_written_once 
        = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT___GEN_10));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__bundleIn_0_d_bits_data_rdata_written_once 
        = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT___GEN_10));
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__error__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__error__DOT__monitor__DOT__inflight_opcodes = 0ULL;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[0U] 
            = __Vconst3811[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[1U] 
            = __Vconst3811[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[2U] 
            = __Vconst3811[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[3U] 
            = __Vconst3811[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[4U] 
            = __Vconst3811[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[5U] 
            = __Vconst3811[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[6U] 
            = __Vconst3811[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[7U] 
            = __Vconst3811[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3802[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3802[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3802[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3802[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3802[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3802[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3802[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3802[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[8U] 
            = __Vconst3802[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[9U] 
            = __Vconst3802[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = __Vconst3802[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = __Vconst3802[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = __Vconst3802[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = __Vconst3802[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = __Vconst3802[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = __Vconst3802[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3811[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3811[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3811[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3811[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3811[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3811[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3811[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3811[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = __Vconst3811[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = __Vconst3811[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = __Vconst3811[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = __Vconst3811[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = __Vconst3811[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = __Vconst3811[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = __Vconst3811[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = __Vconst3811[7U];
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__error__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__error__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__error__DOT__monitor__DOT__inflight_opcodes 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__error__DOT__monitor__DOT___inflight_opcodes_T_2;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[8U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[8U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[9U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[9U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xaU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xaU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xbU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xbU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xcU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xcU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xdU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xdU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xeU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xeU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_opcodes[0xfU] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___inflight_opcodes_T_2[0xfU];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[0U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[1U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[1U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[2U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[2U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[3U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[3U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[4U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[4U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[5U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[5U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[6U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[6U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_opcodes[7U] 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___inflight_opcodes_T_2[7U];
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__enq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT___T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__a_first)
                        ? ((4U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__out_a_bits_opcode))
                            ? 0U : (~ (0x7ffU & (((IData)(0x3fU) 
                                                  << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__out_a_bits_size)) 
                                                 >> 2U))))
                        : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT___T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter 
            = (0x3fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__a_first)
                         ? ((4U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__out_a_bits_opcode))
                             ? 0U : (~ (0x1fffffU & 
                                        (((IData)(0xffU) 
                                          << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__out_a_bits_size)) 
                                         >> 2U)))) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__shift = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__shift = 0U;
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__shift 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT___GEN_8[0U];
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__shift 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT___GEN_8[0U];
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__maybe_full = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_enq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_enq;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__bundleOut_0_a_bits_data_rdata_written_once 
        = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT___GEN_4));
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__repeated_repeater__DOT__saved_mask 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl_auto_out_a_bits_mask;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__repeated_repeater__DOT__saved_mask 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl_auto_out_a_bits_mask;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__monitor__DOT___GEN_84)) 
                                               & (~ 
                                                  (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)))
                                                    : 0U)))));
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__counter_3 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT___T_3) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__counter_3 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__d_first)
                        ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__in_d_bits_opcode))
                            ? (~ (0x7ffU & (((IData)(0x3fU) 
                                             << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__in_d_bits_size)) 
                                            >> 2U)))
                            : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__counter1_3)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__counter_3 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT___T_3) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__counter_3 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__d_first)
                        ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__in_d_bits_opcode))
                            ? (~ (0x7ffU & (((IData)(0x3fU) 
                                             << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__in_d_bits_size)) 
                                            >> 2U)))
                            : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sbypass__DOT__bar__DOT__counter1_3)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1 = 0U;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__bundleOut_0_a_bits_data_rdata_written_once 
        = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT___GEN_4));
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter_2 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT___T_2) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter_2 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__c_first)
                        ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__out_c_bits_opcode))
                            ? (~ (0x7ffU & (((IData)(0x3fU) 
                                             << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__out_c_bits_size)) 
                                            >> 2U)))
                            : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter1_2)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter_2 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT___T_2) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter_2 
            = (0x3fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__c_first)
                         ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__out_c_bits_opcode))
                             ? (~ (0x1fffffU & (((IData)(0xffU) 
                                                 << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__out_c_bits_size)) 
                                                >> 2U)))
                             : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter1_2)));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_enq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__busy_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___T_5) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__busy_1 
            = (0U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__len_1));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__busy = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___T_2) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__busy 
            = (0U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__len));
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_enq;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_enq;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq_io_deq_bits_last;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_last__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq_io_deq_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_data__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_strb__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq_io_deq_bits_strb;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_strb__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__repeated_repeater__DOT__saved_data 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl_auto_out_a_bits_data;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__repeated_repeater__DOT__saved_data 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl_auto_out_a_bits_data;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qa_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qa_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qa_q__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qa_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qd_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qd_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qd_q__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qd_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qa_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qa_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qa_q__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qa_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qd_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qd_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qd_q__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qd_q__DOT___valid_0_T_6)));
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_echo_tl_state_size__v0 = 1U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_len__v0 
            = (0xffU & (~ (0x7fffU & (((IData)(0x7ffU) 
                                       << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_size)) 
                                      >> 3U))));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_len__v0 = 1U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_size__v0 
            = ((3U <= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_size))
                ? 3U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_size));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_size__v0 = 1U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_enq;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx_reset_reg__DOT__reg_) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_enq;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__ram_tl_state_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__ram_tl_state_source__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_enq;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater__DOT__saved_size 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_size;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag_auto_out_wvalid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__maybe_full)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_strb
               [0U] : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq_io_deq_bits_strb));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag_auto_out_wvalid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__maybe_full)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__in_wdeq__DOT__ram_data
               [0U] : vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq_io_deq_bits_data);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_e = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_b = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_c = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_e = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_b = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_c = 0U;
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_e 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___ioX_tx_e_T_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_b 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___ioX_tx_bT_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_c 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___ioX_tx_c_T_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_e 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___ioX_tx_e_T_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_b 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___ioX_tx_bT_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_c 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___ioX_tx_c_T_6);
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_first_1 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___GEN_1));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_first_2 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___GEN_2));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_first_4 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___GEN_4));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_first_1 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___GEN_1));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_first_2 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___GEN_2));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_first_4 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___GEN_4));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__bundleOut_0_a_bits_mask_rdata_written_once 
        = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT___GEN_6));
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_d = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_a = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_d = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_a = 0U;
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_d 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___ioX_tx_d_T_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__tx_a 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___ioX_tx_a_T_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_d 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___ioX_tx_d_T_6);
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__tx_a 
            = (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___ioX_tx_a_T_6);
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_first 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___GEN_0));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_first_3 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___GEN_3));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_first 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___GEN_0));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_first_3 
        = ((IData)(vlTOPp->reset) | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___GEN_3));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceA__DOT__extract__DOT__shift 
        = (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceA__DOT__extract__DOT___GEN_10);
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT__saved_size 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_in_d_bits_size;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_size 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_size;
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_enq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value)));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__do_deq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1)));
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__bundleOut_0_a_bits_mask_rdata_written_once 
        = ((~ (IData)(vlTOPp->reset)) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT___GEN_6));
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_enq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value)));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_deq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value_1 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value_1)));
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__wbeats_latched 
        = ((~ (IData)(vlTOPp->reset)) & ((~ ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__full)) 
                                             & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1_io_deq_valid) 
                                                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___in_awready_T)))) 
                                         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT___GEN_10)));
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__maybe_full = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_enq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__maybe_full = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_enq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_enq;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract__DOT__shift 
        = (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceA__DOT__extract__DOT___GEN_10);
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT__error_1 = 0U;
    } else if ((1U & ((((IData)(1U) << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq_io_deq_bits_id)) 
                       >> 1U) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT___T_26)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT__error_1 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_2_auto_in_becho_real_last)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT___error_1_T));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT__error_0 = 0U;
    } else if ((3U & (((IData)(1U) << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq_io_deq_bits_id)) 
                      & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT___T_26)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT__error_0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_2_auto_in_becho_real_last)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4frag__DOT___error_0_T));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_last_counter = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_ready) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_last_counter 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_last_first)
                        ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_opcode))
                            ? (~ (0x7ffU & (((IData)(0x3fU) 
                                             << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_size)) 
                                            >> 2U)))
                            : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_last_counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_last_counter = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_ready) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_last_counter 
            = (0x3fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_last_first)
                         ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_opcode))
                             ? (~ (0x1fffffU & (((IData)(0xffU) 
                                                 << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_size)) 
                                                >> 2U)))
                             : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_last_counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_enq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value)));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__do_enq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value)));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_burst__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_burst;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_burst__v0 = 1U;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qb_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qb_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qb_q__DOT__valid_1)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qb_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qc_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qc_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qc_q__DOT__valid_1)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qc_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qe_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qe_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qe_q__DOT__valid_1)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qe_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qb_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qb_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qb_q__DOT__valid_1)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qb_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qc_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qc_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qc_q__DOT__valid_1)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qc_q__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qe_q__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qe_q_io_deq_ready)
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qe_q__DOT__valid_1)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qe_q__DOT___valid_0_T_6)));
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_source) 
                     >> 3U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_id__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_counter = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_ready) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_counter 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_first)
                        ? ((4U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_bits_opcode))
                            ? 0U : (~ (0x7ffU & (((IData)(0x3fU) 
                                                  << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_bits_size)) 
                                                 >> 2U))))
                        : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_counter = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_ready) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_counter 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_first)
                        ? ((4U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_bits_opcode))
                            ? 0U : (~ (0x7ffU & (((IData)(0x3fU) 
                                                  << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_bits_size)) 
                                                 >> 2U))))
                        : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_last_counter1)));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_size__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__state = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT___T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__state 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT___T_1)
                ? ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_grant)
                    ? 1U : ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_opcode))
                             ? 2U : 0U)) : ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT___T_2)
                                             ? ((1U 
                                                 & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_opcode))
                                                 ? 2U
                                                 : 0U)
                                             : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT___GEN_1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__state = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT___T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__state 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT___T_1)
                ? ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_grant)
                    ? 1U : ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_opcode))
                             ? 2U : 0U)) : ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT___T_2)
                                             ? ((1U 
                                                 & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d_io_deq_bits_opcode))
                                                 ? 2U
                                                 : 0U)
                                             : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT___GEN_1)));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_addr__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_addr;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_addr__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_enq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value)));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__do_deq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value_1 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value_1)));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_13__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_14__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_15__DOT__ram_extra_id__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_burst__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_burst;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_burst__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_7__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_8__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_9__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_10__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_11__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_12__DOT__ram_extra_id__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__b_count_0 = 0U;
    } else if ((3U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT___T_90) 
                      & ((IData)(1U) << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq_io_deq_bits_id))))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__b_count_0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT___bcount_0_T_1;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__b_count_1 = 0U;
    } else if ((1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT___T_90) 
                      & (((IData)(1U) << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq_io_deq_bits_id)) 
                         >> 1U)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__b_count_1 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT___bcount_1_T_1;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT___value_T_3));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_size__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__d_first_counter_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_io_in_d_valid) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__d_first_counter_1 
            = (0x3fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__d_first_1)
                         ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))
                             ? (~ (0x1fffffU & (((IData)(0xffU) 
                                                 << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_size)) 
                                                >> 2U)))
                             : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__d_first_counter1_1)));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_addr__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_addr;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_addr__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter_3 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT___T_3) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter_3 
            = (0x3fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__d_first)
                         ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))
                             ? (~ (0x1fffffU & (((IData)(0xffU) 
                                                 << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_size)) 
                                                >> 2U)))
                             : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__counter1_3)));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31__DOT__ram_extra_id__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter_3 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT___T_3) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter_3 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__d_first)
                        ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode))
                            ? (~ (0x7ffU & (((IData)(0x3fU) 
                                             << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_size)) 
                                            >> 2U)))
                            : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__counter1_3)));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT____Vlvbound5 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT____Vlvbound5;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_tl_state_source__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT____Vlvbound5 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT____Vlvbound5;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_tl_state_source__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT____Vlvbound5 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT____Vlvbound5;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_tl_state_source__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT____Vlvbound5 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT____Vlvbound5;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_tl_state_source__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT____Vlvbound5 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT____Vlvbound5;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_tl_state_source__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT____Vlvbound5 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT____Vlvbound5;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_tl_state_source__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT____Vlvbound5 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_source;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT____Vlvbound5;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_tl_state_source__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_tl_state_source__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28__DOT__ram_extra_id__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__state = 0U;
    } else if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__qa_q__DOT__valid_1)) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__state 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT___T_1)
                ? 1U : ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT___T_2)
                         ? 2U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT___GEN_2)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__state = 0U;
    } else if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__qa_q__DOT__valid_1)) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__state 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT___T_1)
                ? 1U : ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT___T_2)
                         ? 2U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT___GEN_2)));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater__DOT__saved_size 
            = (7U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_size));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_len__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_len;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_len__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__state = 0U;
    } else if ((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_bits_opcode))) {
        if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT___T_3) {
            vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__state 
                = (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__full) 
                    | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__last))
                    ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject__DOT___state_T_1));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__state = 0U;
    } else if ((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q_io_deq_bits_opcode))) {
        if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT___T_3) {
            vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__state 
                = (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__full) 
                    | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT__last))
                    ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject__DOT___state_T_1));
        }
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_len__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_len;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_len__v0 = 1U;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_2) 
                                               | ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_io_in_d_valid) 
                                                    & (0U 
                                                       == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__d_first_counter_3))) 
                                                   & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT___T_1517))
                                                   ? 1U
                                                   : 0U))));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__inflight_2) 
                                               | ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_io_in_d_valid) 
                                                    & (0U 
                                                       == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT__d_first_counter_3))) 
                                                   & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor__DOT___T_1376))
                                                   ? 1U
                                                   : 0U))));
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_1__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_2__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_3__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_4__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_5__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_6__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__enq_ptr_value;
        }
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT___T_1) 
         & (0ULL == (0x180000000ULL & (QData)((IData)(
                                                      (0x80000000U 
                                                       ^ vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data))))))) {
        if ((1U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v0 
                = (0xffU & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                   [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1]));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v0 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v0 = 0U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v0 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
        if ((2U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v1 
                = (0xffU & (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                    [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1] 
                                    >> 8U)));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v1 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v1 = 8U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v1 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
        if ((4U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v2 
                = (0xffU & (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                    [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1] 
                                    >> 0x10U)));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v2 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v2 = 0x10U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v2 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
        if ((8U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v3 
                = (0xffU & (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                    [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1] 
                                    >> 0x18U)));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v3 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v3 = 0x18U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v3 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
        if ((0x10U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v4 
                = (0xffU & (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                    [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1] 
                                    >> 0x20U)));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v4 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v4 = 0x20U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v4 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
        if ((0x20U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v5 
                = (0xffU & (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                    [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1] 
                                    >> 0x28U)));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v5 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v5 = 0x28U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v5 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
        if ((0x40U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v6 
                = (0xffU & (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                    [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1] 
                                    >> 0x30U)));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v6 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v6 = 0x30U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v6 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
        if ((0x80U & vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb
             [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1])) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v7 
                = (0xffU & (IData)((vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data
                                    [vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value_1] 
                                    >> 0x38U)));
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v7 = 1U;
            vlTOPp->__Vdlyvlsb__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v7 = 0x38U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__srams__DOT__mem__DOT__mem_ext__DOT__ram__v7 
                = (0xfffffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_addr_io_deq_bits_MPORT_data 
                                 >> 3U));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__extract__DOT__state = 0U;
    } else if ((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__extract_io_i_bits_opcode))) {
        if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__extract_io_i_ready) 
             & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB_io_q_sink_io_deq_valid) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__xmit)))) {
            vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__extract__DOT__state 
                = (((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__q_last_count)) 
                    | ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__q_last_count)) 
                       & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__q_last_beats_a))))
                    ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__extract__DOT___GEN_2));
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__extract__DOT__state = 0U;
    } else if ((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__extract_io_i_bits_opcode))) {
        if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__extract_io_i_ready) 
             & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB_io_q_sink_io_deq_valid) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__xmit)))) {
            vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__extract__DOT__state 
                = (((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__q_last_count)) 
                    | ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__q_last_count)) 
                       & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__q_last_beats_a))))
                    ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__extract__DOT___GEN_2));
        }
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_size 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_c_bits_size;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_size 
            = (7U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_c_bits_size));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_opcode 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_c_bits_opcode;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeat_last_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1__DOT__saved_opcode 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_c_bits_opcode;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__r_first) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__r_denied_r = 0U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_opcode 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__hints_auto_in_d_bits_opcode;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT__saved_opcode 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__hints_auto_in_d_bits_opcode;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__d_first_counter = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT___d_first_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__d_first_counter 
            = (0x1fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__d_first_first)
                         ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_in_d_bits_opcode))
                             ? (~ (0xfffffU & (((IData)(0xffU) 
                                                << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_size)) 
                                               >> 3U)))
                             : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer_1__DOT__d_first_counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__d_first_counter = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT___d_first_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__d_first_counter 
            = (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__d_first_first)
                      ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_in_d_bits_opcode))
                          ? (~ (0x3ffU & (((IData)(0x3fU) 
                                           << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_in_d_bits_size)) 
                                          >> 3U))) : 0U)
                      : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer_1__DOT__d_first_counter1)));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB__DOT__r_1 
            = (7U & (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceB_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                     >> 3U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB__DOT__r_1 
            = (7U & (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceB_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                     >> 3U));
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__r_first) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__r_denied_r 
            = (3U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data));
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__r_first) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__r_denied_r 
            = (3U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint_auto_in_rresp));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_id__v0 
            = (0xfU & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_id__v0 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__maybe_full)
                        ? vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq__DOT__ram_id
                       [0U] : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id)));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_ardeq__DOT__value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT___GEN_15))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_id__v0 
            = (0xfU & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag_auto_out_awvalid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_id__v0 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__maybe_full)
                        ? vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4frag__DOT__deq_1__DOT__ram_id
                       [0U] : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id)));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__mem__DOT__axi4buf__DOT__bundleOut_0_awdeq__DOT__value;
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_count = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_d_ready) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_valid))) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_count 
            = (1U & ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_last)) 
                     & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_count))));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27__DOT__ram_extra_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28__DOT__ram_extra_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28__DOT__ram_extra_id__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__source_valid__DOT__io_out_source_valid_0__DOT__output_chain__DOT__sync_0) 
         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__ridx_incremented) 
            != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__widx_widx_gray__DOT__output_chain__DOT__sync_0)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[0U] 
            = (IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_d)) 
                        << 0x14U) | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_e))));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[1U] 
            = ((0xffffff00U & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                         << 0x28U) 
                                        | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                            << 0x14U) 
                                           | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c))))) 
                               << 8U)) | (IData)(((
                                                   ((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_d)) 
                                                    << 0x14U) 
                                                   | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_e))) 
                                                  >> 0x20U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[2U] 
            = ((0xffU & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c))))) 
                         >> 0x18U)) | (0xffffff00U 
                                       & ((IData)((
                                                   (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                                     << 0x28U) 
                                                    | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                                        << 0x14U) 
                                                       | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c)))) 
                                                   >> 0x20U)) 
                                          << 8U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[3U] 
            = (0xffU & ((IData)(((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c)))) 
                                 >> 0x20U)) >> 0x18U));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__source_valid__DOT__io_out_source_valid_0__DOT__output_chain__DOT__sync_0) 
         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__ridx_incremented) 
            != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__widx_widx_gray__DOT__output_chain__DOT__sync_0)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[0U] 
            = (IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_d)) 
                        << 0x14U) | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_e))));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[1U] 
            = ((0xffffff00U & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                         << 0x28U) 
                                        | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                            << 0x14U) 
                                           | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c))))) 
                               << 8U)) | (IData)(((
                                                   ((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_d)) 
                                                    << 0x14U) 
                                                   | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_e))) 
                                                  >> 0x20U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[2U] 
            = ((0xffU & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c))))) 
                         >> 0x18U)) | (0xffffff00U 
                                       & ((IData)((
                                                   (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                                     << 0x28U) 
                                                    | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                                        << 0x14U) 
                                                       | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c)))) 
                                                   >> 0x20U)) 
                                          << 8U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rxInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[3U] 
            = (0xffU & ((IData)(((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_rxc_source__DOT__mem_0_c)))) 
                                 >> 0x20U)) >> 0x18U));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_a = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_a = 0U;
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_a 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_a 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__enq_ptr_value;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__count_1 = 0U;
    } else if ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater_1_io_enq_ready) 
                 | (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__last_1))) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_c_valid))) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__count_1 
            = (1U & ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__last_1)) 
                     & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__count_1))));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__count_1 = 0U;
    } else if ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater_1_io_enq_ready) 
                 | (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__last_1))) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_c_valid))) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__count_1 
            = (1U & ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__last_1)) 
                     & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__count_1))));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_29__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_30__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_31__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_23__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_24__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_25__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_26__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_27__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_28__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_13__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_14__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_15__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_7__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_8__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_9__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_10__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_11__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_12__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_29__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_30__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_31__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_23__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_24__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_25__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_26__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_27__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28__DOT__maybe_full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28__DOT__ram_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_28__DOT__ram_tl_state_size__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_sink__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__enq_ptr_value;
        }
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_denied__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_denied;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_denied__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_param__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_param;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_param__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1_auto_in_d_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_data__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_size__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_source__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_opcode__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_opcode__v0 = 1U;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_84)) 
                                               & (~ 
                                                  ((((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                     & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__mbypass__DOT__bypass_c))) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceE_io_q_sink_io_deq_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << 
                                                       (1U 
                                                        & (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceE_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                                                           >> 0x10U))))
                                                    : 0U)))));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_2 
        = (1U & ((~ (IData)(vlTOPp->reset)) & (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT__inflight_2) 
                                                | (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__monitor_1__DOT___GEN_84)) 
                                               & (~ 
                                                  ((((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_e_bits_sink)) 
                                                     & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass__DOT__bypass_c))) 
                                                    & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceE_io_q_sink_io_deq_valid))
                                                    ? 
                                                   (3U 
                                                    & ((IData)(1U) 
                                                       << 
                                                       (1U 
                                                        & (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceE_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                                                           >> 0x10U))))
                                                    : 0U)))));
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT____Vlvbound6 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_id) 
                     >> 4U));
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT____Vlvbound6;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__ram_extra_id__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__ram_extra_id__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__enq_ptr_value;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__q_last_count = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT___q_last_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__q_last_count 
            = (0x1fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__q_last_first)
                         ? ((IData)(2U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT___q_last_beats_c_T_1))
                         : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT___q_last_count_T_1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__q_last_count = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___q_last_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__q_last_count 
            = (0x1fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__q_last_first)
                         ? ((IData)(2U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___q_last_beats_c_T_1))
                         : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT___q_last_count_T_1)));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__enq_ptr_value;
        }
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22_io_enq_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT____Vlvbound4 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_deq_bits_echo_tl_state_size;
        if ((0x10U >= (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__enq_ptr_value))) {
            vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT____Vlvbound4;
            vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__ram_tl_state_size__v0 = 1U;
            vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__ram_tl_state_size__v0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__enq_ptr_value;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_b = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_c = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_d = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_e = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_b = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_c = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_d = 0U;
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_e = 0U;
    } else {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_b 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_1)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_1));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_c 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_2)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_2));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_d 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_3)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_3));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_e 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_4)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__rx_z_4));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_b 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_1)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_1));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_c 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_2)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_2));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_d 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_3)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_3));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_e 
            = ((0x100000U & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_4)
                ? 0xfffffU : (0xfffffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__rx_z_4));
    }
    if (((0U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__free)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam_io_alloc_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam_io_alloc_bits;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam_io_key;
    }
    if (((0U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__free)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam_io_alloc_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam_io_alloc_bits;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam__DOT__data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam_io_key;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___GEN_14))) {
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_param__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_mask__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_auto_out_a_bits_mask;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_mask__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_auto_out_a_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_data__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__readys_mask_1 = 3U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__idle_3) 
                & (0U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__readys_filter_lo_1)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__readys_mask_1 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT___readys_mask_T_5) 
               | (2U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT___readys_mask_T_5) 
                        << 1U)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_3_0 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__idle_3) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_3_0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__winner_3_0;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_3_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__idle_3) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_3_1 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__winner_3_1;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_1__DOT__repeated_repeater__DOT__saved_source 
            = (0x3fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_in_d_bits_source) 
                        >> 1U));
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__c_first) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__source_r 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__cam_io_key;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__c_first) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__source_r 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__cam_io_key;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___GEN_14))) {
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_param__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_mask__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_auto_out_a_bits_mask;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_mask__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_auto_out_a_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sinkA__DOT__inject_io_i_q__DOT__ram_data__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__readys_mask = 3U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__idle_2) 
                & (0U != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__readys_filter_lo)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__readys_mask 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT___readys_mask_T) 
               | (2U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT___readys_mask_T) 
                        << 1U)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_2_0 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__idle_2) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_2_0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__winner_2_0;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_2_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__idle_2) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__state_2_1 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi4xbar__DOT__winner_2_1;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT___do_enq_T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__do_flow)))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__enq_ptr;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqa__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqb__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqc__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqd__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q_io_enq_ready) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__ram__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__empty)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data
                : vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__ram
               [vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__fq__DOT__ram__DOT__ram_ext__DOT__reg_R0_addr]);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__hqe__DOT__io_deq_q__DOT__ram__v0 = 1U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__formatValid) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__format_r 
            = (7U & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__b2c_data);
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__formatValid) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__format_r 
            = (7U & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__b2c_data);
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__xmit = 0U;
    } else if ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__allowed) 
                 >> 5U) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__f_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__xmit = 3U;
    } else if ((1U & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__forceXmit)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__xmit 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT___xmit_T_1;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__xmit = 0U;
    } else if ((((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__allowed) 
                 >> 5U) & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__f_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__xmit = 3U;
    } else if ((1U & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__forceXmit)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__xmit 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT___xmit_T_1;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_1__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((2U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_1__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_1__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_2__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((4U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_2__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_2__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_3__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((8U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_3__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_3__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_4__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((0x10U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_4__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__ioX_cq_4__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_1__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((2U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_1__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_1__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_2__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((4U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_2__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_2__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_3__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((8U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_3__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_3__DOT___valid_0_T_6)));
    vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_4__DOT__valid_0 
        = ((~ (IData)(vlTOPp->reset)) & ((0x10U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__allowed))
                                          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_4__DOT___wen_T_3)
                                          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__ioX_cq_4__DOT___valid_0_T_6)));
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT___d_first_T) 
         & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__d_first_counter)))) {
        if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__d_cam_sel_match_0) 
             & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_in_d_bits_opcode)))) {
            vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__cam_d_0_denied 
                = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_in_d_bits_denied;
        }
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT___d_first_T) 
         & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__d_first_counter)))) {
        if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__d_cam_sel_match_0) 
             & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_auto_in_d_bits_opcode)))) {
            vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics__DOT__cam_d_0_data = 0ULL;
        }
    }
    if ((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__q_address0_r 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg;
    }
    if ((2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__q_address1_r 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg;
    }
    if ((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__q_address0_r 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg;
    }
    if ((2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__q_address1_r 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg;
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__r_2 
            = (7U & (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                     >> 6U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__r_2 
            = (7U & (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                     >> 6U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__r_5 
            = (0xffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                          >> 0x10U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__r_5 
            = (0xffffU & (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                          >> 0x10U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__r_3 
            = (0xfU & (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                       >> 9U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__r_3 
            = (0xfU & (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                       >> 9U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC__DOT__r_1 
            = (7U & (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                     >> 3U));
    }
    if ((0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__state))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC__DOT__r_1 
            = (7U & (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sourceC_io_q_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg 
                     >> 3U));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__last)))) {
        if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__bundleIn_0_d_bits_data_masked_enable_0) {
            vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__bundleIn_0_d_bits_data_rdata_0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_data;
        }
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_addr__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_address;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_addr__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2__DOT__repeated_repeater__DOT__saved_address 
            = (0x1fffU & vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__atomics_auto_out_a_bits_address);
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__r_holds_d = 0U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_2__DOT__repeated_repeater__DOT__saved_address 
            = (0x1fffU & vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_address);
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility__DOT__deq_ptr_value = 0U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__deq_ptr_value = 0U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__source_valid__DOT__io_out_source_valid_0__DOT__output_chain__DOT__sync_0) 
         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__ridx_incremented) 
            != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__widx_widx_gray__DOT__output_chain__DOT__sync_0)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[0U] 
            = (IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_d)) 
                        << 0x14U) | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_e))));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[1U] 
            = ((0xffffff00U & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                         << 0x28U) 
                                        | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                            << 0x14U) 
                                           | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c))))) 
                               << 8U)) | (IData)(((
                                                   ((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_d)) 
                                                    << 0x14U) 
                                                   | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_e))) 
                                                  >> 0x20U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[2U] 
            = ((0xffU & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c))))) 
                         >> 0x18U)) | (0xffffff00U 
                                       & ((IData)((
                                                   (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                                     << 0x28U) 
                                                    | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                                        << 0x14U) 
                                                       | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c)))) 
                                                   >> 0x20U)) 
                                          << 8U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[3U] 
            = (0xffU & ((IData)(((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c)))) 
                                 >> 0x20U)) >> 0x18U));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__source_valid__DOT__io_out_source_valid_0__DOT__output_chain__DOT__sync_0) 
         & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__ridx_incremented) 
            != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__widx_widx_gray__DOT__output_chain__DOT__sync_0)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[0U] 
            = (IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_d)) 
                        << 0x14U) | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_e))));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[1U] 
            = ((0xffffff00U & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                         << 0x28U) 
                                        | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                            << 0x14U) 
                                           | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c))))) 
                               << 8U)) | (IData)(((
                                                   ((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_d)) 
                                                    << 0x14U) 
                                                   | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_e))) 
                                                  >> 0x20U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[2U] 
            = ((0xffU & ((IData)((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c))))) 
                         >> 0x18U)) | (0xffffff00U 
                                       & ((IData)((
                                                   (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                                     << 0x28U) 
                                                    | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                                        << 0x14U) 
                                                       | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c)))) 
                                                   >> 0x20U)) 
                                          << 8U)));
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__tx__DOT__txInc_sink__DOT__io_deq_bits_deq_bits_reg__DOT__cdc_reg[3U] 
            = (0xffU & ((IData)(((((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_a)) 
                                   << 0x28U) | (((QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_b)) 
                                                 << 0x14U) 
                                                | (QData)((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__rx__DOT__io_txc_source__DOT__mem_0_c)))) 
                                 >> 0x20U)) >> 0x18U));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__b_count_0 = 0U;
    } else if ((3U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT___T_90) 
                      & ((IData)(1U) << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq_io_deq_bits_id))))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__b_count_0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT___bcount_0_T_1;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__b_count_1 = 0U;
    } else if ((1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT___T_90) 
                      & (((IData)(1U) << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq_io_deq_bits_id)) 
                         >> 1U)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__b_count_1 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT___bcount_1_T_1;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__do_enq;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__maybe_full = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__do_enq) 
                != (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__do_deq))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__do_enq;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__enq_ptr_value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT___GEN_8))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq_io_enq_bits_resp;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT__ram_resp__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__enq_ptr_value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT___GEN_8))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT__ram_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_source) 
                     >> 3U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__q_bdeq__DOT__ram_id__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_count = 0U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__mbypass_auto_out_d_ready) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_valid))) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_count 
            = (1U & ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_last)) 
                     & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_count))));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__enq_ptr_value;
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__count = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT___T) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__count 
            = (1U & ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__last)) 
                     & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget__DOT__count))));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__enq_ptr_value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___GEN_10))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq_io_enq_bits_resp;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_resp__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___GEN_10))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_auto_in_d_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_data__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___GEN_10))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq_io_enq_bits_last;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_last__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_extra_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_echo_extra_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_echo_extra_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_data_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_resp_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_resp__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1_auto_in_recho_tl_state_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_echo_tl_state_size__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__enq_ptr_value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__last)))) {
        if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__bundleIn_0_d_bits_data_masked_enable_0) {
            vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__bundleIn_0_d_bits_data_rdata_0 
                = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_data;
        }
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT__d_first_counter = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT___d_first_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT__d_first_counter 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT__d_first_first)
                        ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_opcode))
                            ? (~ (0x7ffU & (((IData)(0x3fU) 
                                             << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_size)) 
                                            >> 2U)))
                            : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__fixer__DOT__d_first_counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT__maybe_full = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT___do_enq_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT__maybe_full 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__tl2axi4__DOT__deq__DOT___do_enq_T;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT__ram_echo_tl_state_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT__ram_echo_tl_state_size__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq_io_enq_bits_last;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_last__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_data__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_strb__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_mask;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_strb__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__maybe_full)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_data
               [0U] : vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_data);
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq_io_deq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb__v0 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__maybe_full)
                ? vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__deq__DOT__ram_strb
               [0U] : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_mask));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__ram_strb__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleOut_0_wdeq__DOT__value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq_io_enq_bits_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4_1__DOT__queue_arw_deq__DOT__ram_id__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq_io_enq_bits_last;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__ram_last__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__ram_data__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT___GEN_9))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__ram_strb__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_mask;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__deq__DOT__ram_strb__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_burst__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_enq_bits_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_size__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_echo_tl_state_size__v0 
            = (7U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_size));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_echo_tl_state_size__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_len__v0 
            = (0xffU & (~ (0x7fffU & (((IData)(0x7ffU) 
                                       << (7U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_size))) 
                                      >> 3U))));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_len__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq_io_enq_bits_id;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_id__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT___T) 
         & (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeat_last)))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater__DOT__saved_source 
            = (0x3fU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_source) 
                        >> 1U));
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_id_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_id__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_id__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__enq_ptr_value;
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__value_1 = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__do_deq) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__value_1 
            = (1U & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__value_1)));
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT___GEN_18))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_addr__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics_auto_out_a_bits_address;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__tl2axi4__DOT__queue_arw_deq__DOT__ram_addr__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT___GEN_10))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_source) 
                     >> 3U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__ram_id__v0 = 1U;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_6__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_7__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_8__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_9__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_10__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_11__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_12__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_13__DOT__enq_ptr_value;
    }
    if (((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__full)) 
         & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14_io_enq_valid))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4buf__DOT__bundleIn_0_rdeq__DOT__ram_last_io_deq_bits_MPORT_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_last__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__ram_last__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_14__DOT__enq_ptr_value;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT___GEN_8))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT__ram_resp__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq_io_enq_bits_resp;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT__ram_resp__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_sink__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_denied__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_denied;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_denied__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_param__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_param;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_param__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_data__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1_auto_in_d_bits_data;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_data__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_size__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_size;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_size__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_source__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_source;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_source__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT___GEN_14))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_opcode__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__widget_1__DOT__repeated_repeater_io_deq_bits_opcode;
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__chiplink__DOT__sinkD__DOT__d__DOT__ram_opcode__v0 = 1U;
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT___d_first_T) 
         & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__d_first_counter)))) {
        if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__d_cam_sel_match_0) 
             & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_opcode)))) {
            vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__cam_d_0_denied 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_denied;
        }
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT___d_first_T) 
         & (0U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__d_first_counter)))) {
        if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__d_cam_sel_match_0) 
             & (1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_opcode)))) {
            vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__atomics__DOT__cam_d_0_data 
                = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_auto_in_d_bits_data;
        }
    }
    if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT__maybe_full)
          ? (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT___do_enq_T)
          : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT___GEN_8))) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT__ram_id__v0 
            = (1U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_source) 
                     >> 3U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT__ram_id__v0 = 1U;
    }
    if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT___do_enq_T) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_last__v0 
            = ((1U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__d_last_counter)) 
               | (0U == ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_opcode))
                          ? (7U & (~ (0x3ffU & (((IData)(0x3fU) 
                                                 << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__xbar_1_auto_in_d_bits_size)) 
                                                >> 3U))))
                          : 0U)));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__fpga__DOT__axi42tl__DOT__deq__DOT__ram_last__v0 = 1U;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT__d_first_counter = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT___d_first_T) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT__d_first_counter 
            = (0xfU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT__d_first_first)
                        ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_opcode))
                            ? (~ (0x7ffU & (((IData)(0x3fU) 
                                             << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_size)) 
                                            >> 2U)))
                            : 0U) : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__fixer__DOT__d_first_counter1)));
    }
    if (vlTOPp->reset) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__count = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT___T) {
        vlTOPp->__Vdly__TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__count 
            = (1U & ((~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__last)) 
                     & ((IData)(1U) + (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget__DOT__count))));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__d_last_counter = 0U;
    } else if ((((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_opcode))
                  ? (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__deq__DOT__maybe_full))
                  : (~ (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__q_bdeq__DOT__maybe_full))) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_auto_in_d_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__d_last_counter 
            = (7U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__d_last_first)
                      ? ((1U & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_opcode))
                          ? (~ (0x3ffU & (((IData)(0x3fU) 
                                           << (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar_1_auto_in_d_bits_size)) 
                                          >> 3U))) : 0U)
                      : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__axi42tl__DOT__d_last_counter1)));
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__bundleIn_0_awready_REG 
        = (3U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__state));
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__bundleIn_0_wready_REG 
        = (4U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__state));
    if (vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__Uregs__DOT__rf_push_pulse) {
        vlTOPp->__Vdlyvval__TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__Uregs__DOT__receiver__DOT__fifo_rx__DOT__rfifo__DOT__ram__v0 
            = (0xffU & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__Uregs__DOT__receiver__DOT__rf_data_in) 
                        >> 3U));
        vlTOPp->__Vdlyvset__TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__Uregs__DOT__receiver__DOT__fifo_rx__DOT__rfifo__DOT__ram__v0 = 1U;
        vlTOPp->__Vdlyvdim0__TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__Uregs__DOT__receiver__DOT__fifo_rx__DOT__rfifo__DOT__ram__v0 
            = vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__luart__DOT__muart__DOT__Uregs__DOT__receiver__DOT__fifo_rx__DOT__top;
    }
    vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__bundleOut_0_penable_REG 
        = ((2U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__state)) 
           | (4U == (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__axi42apb__DOT__state)));
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__readys_mask = 3U;
    } else if (((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__latch) 
                & (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__widget_2_auto_in_d_valid))) {
        vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT__readys_mask 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT___readys_mask_T) 
               | (2U & ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__asic__DOT__chipMaster__DOT__xbar__DOT___readys_mask_T) 
                        << 1U)));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_16__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_17__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_18__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_19__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_20__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_21__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank_1__DOT__QueueCompatibility_22__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_1__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_2__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_3__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_4__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_5__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_6__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_16__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_17__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_18__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_19__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_20__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_21__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__deq_ptr_value 
            = ((IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT__wrap_1)
                ? 0U : (IData)(vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4yank__DOT__QueueCompatibility_22__DOT___value_T_3));
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT__deq_ptr_value 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_15__DOT___value_T_3;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT__deq_ptr_value 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_0__DOT___value_T_3;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT__deq_ptr_value 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_1__DOT___value_T_3;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT__deq_ptr_value 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_2__DOT___value_T_3;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT__deq_ptr_value 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_3__DOT___value_T_3;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT__deq_ptr_value 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_4__DOT___value_T_3;
    }
    if (vlTOPp->reset) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__deq_ptr_value = 0U;
    } else if (vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__do_deq) {
        vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT__deq_ptr_value 
            = vlTOPp->TestHarness__DOT__ldut__DOT__fpga__DOT__axi4deint__DOT__qs_queue_5__DOT___value_T_3;
    }
}
